PERFORMANCE ANALYSIS OF DIFFERENT NEURAL NETWORK ARCHITECTURE FOR BRAIN ACTIVITY

Abstract

An ANN is a kind of computing system that simulates the human brain's information processing capabilities by modelling individual neural connections. Self-learning and data-computing ANNs are built from thousands of individual processing neurons with input and output modules. Realising the enormous neuron system in hardware is a challenging challenge. Computing that mimics the structure and behaviour of the human brain is called neuromorphic computing. Devices that do calculations using physical artificial neurons are referred to as neuromorphic computers or chips. In recent years, the term "neuromorphic" has come to be used to describe hardware and software systems that simulate neural networks on analogue, digital, or mixed-mode VLSI. The project focuses on using the Xilinx integrated system environment (ISE) 14.7 software for the design and implementation of multiple input perceptron devices. The proposed research work aims to get a better understanding of how various neural networks in the brain function by studying their underlying technology. The design scales well and takes in a wide range of inputs (8, 16, 32, 64), all while adhering to the multi-layer ANN, CNN, and RNN designs. Each ANN block consists of eight neurons; hence the whole design is divided among eight parallel ANN blocks. It is possible to teach a recurrent neural network (RNN) to remember past data sequences and to learn new ones. The inherent recurrence of an RNN makes it difficult to fully parallelize all calculations. The study focused on the finite state machine (FSM) design and synthesis using various field programmable gate array (FPGA) hardware to create and simulate a fully RNN chip that processes 64 neurons in three hidden layers. The hardware utilisation rate for the device is provided in the device utilisation report for the chip's implementation. Device hardware includes the number of constrained IOBs, gated clocks (GCLKs), and input LUT slices used in the design implementation. Timing information reveals the maximum frequency and combined delay.